COMPANY   |   PRODUCTS   |    NEWS    |   IP LICENCING   |    ASIC DESIGN   |    CONTACT US   
HOME > IP LICENSING > IP CORES & MEGA CELLS > Data Storage DATA STORAGE  
 

IP LICENSING
LICENSING
DELIVERABLE
SUPPORT
IP CORES & MEGA CELLS
A to D Converters
D to A Converters
Data Storage
Error Correction
Ethernet Networking
I/O Cell & Peripherals
Memory Access Controllers
Micro-Controllers
Micro Cells (Analog)
Phase Locked Loop
Serdes
Serial ATA



SERVO BLOCK MEGACELL

FEATURES

  • Asynchronous clocking (i.e. no phase or frequency lock to servo data), separate frequency synthesizer.
  • Oversampling rates up to 22x.
  • Raw data serial interface (SDATA, SPOL), to accommodate different HDD ASIC architectures.
  • 8 bit NRZ Data Interface for Index/Gray and Bursts transmision assures minimum HDD ASIC logic.
  • Programmable 4, 5 or 6 Bursts accumulation.
  • Programmable AM detection logic (up to 4 transitions within the AM window, including no transition).
  • Pogrammable Index/Gray data field order.
  • Programmable Index/Gray code data pattern and bit length.
  • Programmable Index/Gray code symbol decoding.
  • Programmable error correction/detection on Index and Gray code data.
  • Automatic binary decode of Gray coded data.
  • Programmable linear/non-linear modes for AGC block.
  • Programmable Preamble Detect modes depending on the search state the drive is in.
  • 8 bit TestBus for easy and full testability.

SYSTEM OVERVIEW

BACK


request product info by email
Copyright © 2002 - Ldic, All Rights Reserved