PBUFFER ACCESS CONTROLLER

FEATURES

• 8K x 32-bit internal buffer SRAM
• Host and disk channels with 32-byte FIFOs
• Buffer is direct-memory-mapped, byte-writable
• Independent host auto-read and auto-write pointers
• Data Flow (DF) data flow control

SYSTEM OVERVIEW

Block Diagram

The BAC controls the buffer SRAM interface. The Flash Interface Controller controls access to external Flash chips. The Flash is accessible only to the CPU, through the Cache block. The buffer is accessed primarily by the host interface, disk and DICE blocks for user data, but can also be accessed by the CPU. The CPU can execute from the buffer as well as use it for data storage, however primary execution is intended to be from Flash or dedicated on-chip SRAM. For convenience, the entire buffer RAM is direct-memory-mapped. The Buffer Access Controller (BAC) arbitrates access to the data buffer between the host block (PCMCIA), disk interface, error correction interface, and the CPU.

BUFFER ACCESS CONTROLLER OVERVIEW

The Buffer Access Controller's function is to control the data flow to and from the data buffer. Its other functions include memory segmentation control and channel interfaces. This block interfaces with the PCMCIA, DC, DICE and CPU blocks to provide access to the buffer.

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