LC15-TR03 - Serial ATA PHY
Serial ATA Rev.1 compliant Gen1 physical layer. Bit rate ready for 3Gb/s Gen2.
Frequency synthesizer for ASIC clock generation of 150 MHz.
Built in transmission PLL circuits.
Parallel 10b interface based on SAPIS specification Rev. 0.9
Optional 20bit transmit data (two 10bit 8b/10b encoded characters).
Bidirectional TBC (transmit byte clock)
25MHz Crystal Oscillator
Read/write serial port interface to program the transmission and receive characteristics.
Power Monitor for glitch free Power Off/On cycles.
Power management modes: PARTIAL, SLUMBER , STOP.
Analog loop-back test mode
Device status to Link layer
Low Power consumption, less than TBDmW
Operates at 1.8V supply voltage
LD-LLC-0001-050 - Serial ATA IP CORE
Verliog RTL codes
Estimated gate count 50K
Serial ATA rev1 compliant – Generation 1 Host and Device.
ATA6 compliant Drive interface Host and Device.
Supports 66MHz, 100MHz, 133MHz and 150MHz parallel ATA speed.
Parallel ATA HOST to Serial ATA Interface
Serial ATA to Parallel ATA Device Interface
Serial interface to external serial EEPROM
Big Drive Interfacing- 48 bit block Addressing.
OOB COMRESET and COMAWAKE Detection.
OOB COMINIT and COMWAKE Generation.
8B/10B Encoding and Decoding.
Separate Cont and Data Scramblers to reduce EMI
32 bit Internal Buses for Encoding/Decoding/CRC Generating/Checking and Scrambling.
Ultra-DMA with separate 16 bit CRC Generator.
Primitive Decoder with auto Task File Updating.
Dual 1024 byte Transmit/Receive FIFO’s for over run prevention.
Auto Inserted Hold Primitives to prevent under runs.
Power Monitor for glitch free Power Off/On cycles.
Power management modes (Partial and Slumber).
LDS7011 - SERIAL ATA-IDE, Gen 1
Serial ATA rev1 compliant- Generation 1 Target.
ATA6 compliant Drive interface Host.
Big Drive Interfacing- 48 bit block Addressing.
OOB COMRESET and COMAWAKE Detection.
OOB COMINIT and COMWAKE Generation.
8B/10B Encoding and Decoding.
Separate Cont and Data Scramblers.
32 bit Internal Buses for Encoding/Decoding/CRC Generating/Checking and Scrambling.
Ultra-DMA with separate 16 bit CRC Generator.
15X PLL for Bit Clock Generation- 100 MHz REFCLOCK.
Clock Recovery PLL for Deserializer and Decoder circuits.
Primitive Decoder with auto Task File Updating.
Dual 256 Double Word Transmit/Receive FIFO’s for over run prevention.
Auto Inserted Hold Primitives to prevent under runs.
Receiver impedance equalization for best system performance.
Power Monitor for glitch free Power Off/On cycles.
Power Management modes activated by the PMREQ Primitives.
