LDS7011 - TRANSCIEVER AND SERIAL ATA CONTROLLER
Serial ATA rev1 compliant - Generation 1 Target.
ATA6 compliant Drive interface Host.
Supports 66MHz, 100MHz, 133MHz and 150MHz parallel ATA speed.
Parallel ATA HOST to Serial ATA Interface
Serial ATA to Parallel ATA Device Interface
Built in PHY
Programmable PHY serial optimization through jumpers, serial interface or external serial EEPROM
Big Drive Interfacing- 48 bit block Addressing.
8B/10B Encoding and Decoding.
Separate Cont and Data Scramblers.
32 bit Internal Buses for Encoding/Decoding/CRC Generating/Checking and Scrambling.
Dual 1024 byte Transmit/Receive FIFO's for over run prevention.
Low Power, less than 800mW.

NEPTUNE - PCI-X ADAPTOR TO QUAD SERIAL ATA RAID CONTROLLER
PCI-X/PCI 32 or 64 bit, 33MHz, 66MHz, 100MHz, 133MHz Bus Interface Supports DMA Bus Master Interface
4 independent Scatter/Gather DMA Engines
Four Independent 1Kbyte FIFOES for full speed (1Gbyte/sec) operation.
Supports up to a 1Mx8bit Flash EEPROM for BIOS/Boot Loader
Big Drive Interfacing- 48 bit block Addressing.
OOB COMINIT and COMWAKE Generation.
8B/10B Encoding and Decoding.
32 bit Internal Buses for Encoding/Decoding/CRC Generating/Checking and Scrambling.

ECLIPSE - iSCSI COMMUNICATION PROCESSOR
10 or 1 Gbps Ethernet 802.3 interface controller.
Embedded Quad Phy for 10Gbps Ethernet Support.
Built in DDR SDRAM controller. Supports up to 4GBytes of External Dual Data Rate Fast Synchronous Dynamic RAM memory
Optional PCI 33/66 operational mode
8 DMA channels.
Internal 256 bit high speed bus operates at over 5GBytes per second
Standard support of XTERM login through either the 10/100 or 10/1G
Ethernet ports Diagnostic 10/100 Ethernet Port
300Mip MIPs CPU based Engine
3 separate channels of 1.2/2.4GBps serial ATA, GEN1 or GEN2 drive interface including independent PHYs and serial controllers.
Supports up to 6 serial disk drives directly with no external components.
128K Internal Cache Memory

LC15-TR03 - Serial ATA PHY
Serial ATA Rev.1 compliant Gen1 physical layer. Bit rate ready for 3Gb/s Gen2.
Frequency synthesizer for ASIC clock generation of 150 MHz.
Built in transmission PLL circuits.
Parallel 10b interface based on SAPIS specification Rev. 0.9
Optional 20bit transmit data (two 10bit 8b/10b encoded characters).
Bidirectional TBC (transmit byte clock)
25MHz Crystal Oscillator
Read/write serial port interface to program the transmission and receive characteristics.
Power Monitor for glitch free Power Off/On cycles.
Power management modes: PARTIAL, SLUMBER , STOP.
Analog loop-back test mode
Device status to Link layer
Low Power consumption, less than TBDmW
Operates at 1.8V supply voltage

LD-LLC-0001-050 - Serial ATA IP CORE
Verliog RTL codes
Estimated gate count 50K
Serial ATA rev1 compliant – Generation 1 Host and Device.
ATA6 compliant Drive interface Host and Device.
Supports 66MHz, 100MHz, 133MHz and 150MHz parallel ATA speed.
Parallel ATA HOST to Serial ATA Interface
Serial ATA to Parallel ATA Device Interface
Serial interface to external serial EEPROM
Big Drive Interfacing- 48 bit block Addressing.
OOB COMRESET and COMAWAKE Detection.
OOB COMINIT and COMWAKE Generation.
8B/10B Encoding and Decoding.
Separate Cont and Data Scramblers to reduce EMI
32 bit Internal Buses for Encoding/Decoding/CRC Generating/Checking and Scrambling.
Ultra-DMA with separate 16 bit CRC Generator.
Primitive Decoder with auto Task File Updating.
Dual 1024 byte Transmit/Receive FIFO’s for over run prevention.
Auto Inserted Hold Primitives to prevent under runs.
Power Monitor for glitch free Power Off/On cycles.
Power management modes (Partial and Slumber).