+5V, +8V Current Bias/Current Sense Architecture
+3V, -3V Differential Current Bias-Voltage Sense Architecture
+3.3V Current Bias/Current Sense Architecture
+5V Current Bias/Current Sense Architecture

LD3301 - 5V or 3.3V GMR Head Preamplifier
5V or 3.3V Supply
Current Bias/Current Sense Architecture
3.3V CMOS compatible Logic Interface
Power management
Integrated reference resistor
Single-ended input to reader with one side grounded externally
Differential read output

LD3500 - 5V MR Head Preamplifier
5V only supply voltage
500MHz Read Bandwidth
One side grounded input, fully differential output
Unselected read/write heads at GND potential
Head unsafe fault detection for both read and write
Programmable write damping resistor (3-bits)
PECL no flip-flop
Serial port interface with write and readback register access.
Power fault protection
Only one external component: Rref
Rail to rail head swing
Servo write (half bank, all bank write)
Power management modes

LD3514 - +5V, +8V GMR Head Preamplifier
Current Bias/Current Sense Architecture
5V and 8V supply
3 line serial interface with readback (3.3V CMOS compatible)
(optional 2 line serial port)
Power management modes
On-chip temperature monitor
Internal reference resistor (2Kohm) (optional)
Head unsafe fault detection for both read and write
Fast recovery mode