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LC25GR00-04/-08 - The PHY-er-Chip
2.5Gbits/Sec Fiber Channel Repeater
4/8-port Repeater with daisy chain link
Optional Advance PRML data and clock recovery
Maximum data jitter of 70ps
Maximum propagation bypass delay of 3.0ns
Exceed MJS-10 specification performance
Lowest power consumption at 2.5Gb/S, 500mW max
Fully compliant with ANSI-X3T11 Fiber Channel Specification
Fully scalable technology path toward 10Gb/S
Programmable Intelligent Bypass and auto-connect controller
Advance 0.18micron CMOS technology
84-pin or 100-pin PQFP package

LC25TR00-20 -
      LSI Communication 2.5Gb/S Ethernet Transceiver
      LSI Communication 2.12Gb/S Fiber Channel Transceiver

2.12/1.06 Gbit/S Fiber Channel Transceiver
2.5/1.25 Gbit/S Ethernet Transceiver
Advance optional PRML data and clock recovery
Auto detectable/switchable full or half speed
Maximum serial data output random jitter (RMS) 4.0ps
Maximum serial data output deterministic jitter (p-p) 25.0ps
Maximum data output total jitter (p-p) in loop back mode 1.8ns
Data Acquisition lock time at 2.5Gb/S is 1000 Bit Clock
Lowest power consumption at 2.5Gb/S, 550mW max
Fully compliant with 802.3z Ethernet Specification
Fully scalable technology path toward 10Gb/S Ethernet
Total Power dissipation at 2.5Gb/S is 2.0W
Advance 0.18micron CMOS technology
80-pin or 100-pin EDQUAD package

LD9004 - 4-port 10/100/1000Mbps Layer 2 Ethernet Switch
Supports four 10/100/1000 Mbps Ethernet ports with GMII/MII interface.
IEEE 802.3ab CSMA/CD Compliant
Full and half duplex mode of operation.
Speed and Duplex mode auto-negotiation through MDIO.
Self address learning mechanism supports 512 MAC address.
Automatic address aging with 300 seconds default.
1Mbit packet buffer memory embedded
SPI interface employed to communicated with MCU.
IEEE802.3ab flow control for full duplex operation.
Supports Store-and-Forward mode of operation.
0.18 micron, 1.8V CMOS technology packaged in 160-pin PQFP.
3.3V I/O.


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