540
Ms/s signed 6-bit flash ADC (Cell Specification)
The ADC is able to convert
the analog input signal into a signed 2's complement 6 bit digital word for
further processing. It uses a flash architecture and interpolating comparator
preamplifiers, and is destined mainly for disk drive read or communications
channels.
Features:
- Resolution: 6 bit
- Maximum conversion rate:
540Ms/s
- Differential analog input
voltage range: 1.28Vp-p (centered on 1.1Vdc)
- Integral linearity error:
0.5LSB
- Differential linearity
error: 0.5LSB
- Equivalent Bit Number:
5.3 bits
- Output data format: 2's
complement
- Pipelined delay (ADC
latency): 1 clock cycle
- External reference input
voltages: 1.46V and 0.74V (1.1V +/- 0.36V)
- Supply voltage: 1.8V,
+/-10%
- Dynamic supply current:
60mA, typ.
- Total power dissipation:120mW
- Power down consumption:
1mA, max.
- Operating temperature:
0 - 70oC
- 0.18mm
Digital CMOS Process